1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods therefor.
The present application claims priority on Japanese Patent Application Nos. 2008-50527, filed Feb. 29, 2008 and 2008-307403, filed Dec. 2, 2008, the contents of which are incorporated herein by reference.
2. Description of Related Art
Semiconductor devices serving as dynamic random-access memories (DRAM) are constituted of memory cells including transistors and capacitors. Due to current tendencies for developing semiconductor devices having fine structures, it is necessary to further reduce sizes of transistors, which in turn cause problems of short-channel effects of transistors apparently. As sizes of memory cells included in large-scale dynamic random-access memories become smaller, channel lengths of transfer-gate transistors must be reduced correspondingly, wherein as S values of transfer-gate transistors increase, memory cells must be degraded in terms of retentions and write characteristics.
As one countermeasure against short-channel problems of transistors, trench-gate transistors having three-dimensional structures of channels have been developed to improve refresh characteristics of memory cells. Trench-gate transistors are designed to increase channel lengths by effectively using the boundaries of three-dimensional trenches, which are formed on silicon substrates, as channels.
By adopting the above trench-gate structure used in trench-gate transistors (which are each referred to as RCAT, namely “Recess Channel Access Transistor”), it is possible to cope with short-channel problems of transistors and to improve refresh characteristics of memory cells. Due to the trench-gate structure, it is possible to substantially increase channel lengths and to thereby reduce channel doses, whereby it is possible to improve refreshing effects by way of electric-field relaxation of PN junctions in source/drain regions.
Recently, silicon layers are formed above source/drain regions of transistors in accordance with selective epitaxial growth processes and are used as source/drain regions in order to reduce short-channel effects.
In the manufacturing method of semiconductor devices having the trench-gate structure, it is necessary to perform preprocessing so as to remove thermal oxide films and natural oxide films from silicon substrates (used for forming silicon epitaxial layers) during selective epitaxial growth processes.
The present inventor has recognized the following problems, which will be described with reference to FIGS. 8 to 11.
FIG. 8 shows that an embedded insulating film 103 is formed using a high-density plasma chemical vapor deposition (HDP-CVD) film, a CVD film fabricated by CVD, or a spin-on dielectric (SOD) film fabricated by a spinning application, wherein it is embedded in a silicon substrate 101 so as to form an element separation region M1 for defining activate regions K1.
Channels (or trenches) 108 are formed in the silicon substrate 101; then, a thermal oxide film 102 serving as a gate insulating film is formed on the silicon substrate 101 and inside the channels 108; furthermore, gate electrodes 106 composed of wiring materials including polysilicon layers 104 and metal layers 109 are embedded in the channels 108. In addition, silicon nitride films 107 are formed on the gate electrodes 106. In this connection, channels 108a are formed in the embedded insulating film 103 defining the element separation region M1, wherein polysilicon layers 104a and metal layers 109a are formed using the same materials as the polysilicon layers 104 and the metal layers 109 in the gate electrodes 106.
In the selective epitaxial growth process adapted to the surface of the silicon substrate 101, it is necessary to perform preprocessing for removing the thermal oxide film 102 and its natural oxide film in order to expose the surface of the silicon substrate 101. As preprocessing, wet etching is performed using dilute hydrofluoric acid (DHF). Various methods for etching silicon substrates have been disclosed in various documents such as Patent Documents 1-3.    Patent Document 1: Japanese Unexamined Patent Application Publication No. H06-124944    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-216242    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2002-43543
When the semiconductor device of FIG. 8 is subjected to wet etching as shown in FIG. 9, the thermal oxide film 102 and its natural oxide film are removed from the surface of the silicon substrate 101 while the embedded insulating film 103 forming the element separation region M1 is simultaneously etched so that a recess 103a is formed on the surface of the embedded insulating film 103. Since the embedded insulating film 103 is composed of an oxide silicon film whose wet etching rate is five to ten times higher than that of the thermal oxide film 102, such as the HDP-CVD film, the CVD film, and the SOD film, the depth of the recess 103a must be larger than the thickness of the thermal oxide film 102.
Due to some trouble occurring in a selective epitaxial growth device such that the silicon substrate 101 is neglected for a long time after preprocessing, another natural oxide film may be unexpectedly formed on the surface of the silicon substrate 101 as shown in FIG. 10. This requires another preprocessing in which the embedded insulating film 103 of the element separation region M1 must be further etched so as to further increase the recess 103a, causing partial exposure of the polysilicon layers 104a from the recess 103a. 
Due to the selective epitaxial growth process as shown in FIG. 11, “unwanted” silicon epitaxial layers 105a are additionally formed via the polysilicon layers 104a and are connected to “normal” silicon epitaxial layers 105. This causes short-circuiting between the silicon epitaxial layers 105 and the polysilicon layers 104a formed on the element separation region M1.